As dot matrix type display devices, liquid crystal display devices are used in various devices such as a personal computer due to their advantages of thinness, light weight, and low power. Color liquid crystal display devices with an active matrix system in particular, which are advantageous for controlling image quality with high definition, have become dominant.
The liquid crystal display module of the liquid crystal display device includes a liquid crystal panel (LCD panel), a control circuit (which will be hereinafter referred to as a controller) constituted from a semiconductor integrated circuit (which will be hereinafter referred to as an IC), scanning side driving circuits (which will be referred to as scanning drivers) and data side driving circuits (which will be referred to as data drivers), both constituted from ICs. Due to the higher definition of the picture quality of the liquid crystal panel and the larger size of the liquid crystal panel, the transfer speed of display data has become faster. When the transfer speed of the display data becomes faster, the frequencies of inversion of a clock signal and the display data in a unit of time will increase. When the clock signal and the display data are binary voltage signals (which will be referred to as CMOS signals) the amplitude of which changes (inverts) according to whether the signals are at a supply voltage level (“H” level) or a ground level (“L” level), there is a problem in which EMI (Electro Magnetic Interference) noise and current consumption increase in wiring between the controller and the data drivers through which the clock signal and the display data are transferred.
As one method of solving this problem, a method is used in which primary inversion of the logic of display data constituted by a CMOS signal is performed by a primary data inversion circuit of a transfer source according to a data inversion signal INV, thereby reducing the frequency of inversion in the entire transfer wiring, and then secondary inversion for returning the logic of the display data to the original logic is performed by a secondary data inversion circuit of a transfer destination (refer to Patent Document 1, for example). In this method, when display data constituted by the CMOS signals having a 18-bit width of 6 bits by 3 dots (R, G, B) are transferred, a logic inversion change before or after each bit in the 18-bit display data from the “H” level to the “L” level or from the “L” level to the “H” level is detected by the controller of the transfer source. Then, when the number of the changed bits is 13 bits that is larger than half of the number of 18 bits, for example, a data inversion signal INV at the “H” level is generated. Then, the logics of 18 bits are inverted at the primary data inversion circuits for the 18 bits provided near output terminals of the controller, according to this data inversion signal INV. With this arrangement, in the transfer wiring with the 18-bit width, 13 bits of the 18 bits are not inverted, so that only five bits are inverted. The frequencies of inversion can be reduced, so that the EMI noise and the current consumption can be reduced. Then, in order to return the display data with the 18 bit width to its original logic state, the display data are inverted again to the logics of the 18 bits by the secondary data inversion circuits for the 18 bits, provided near input terminals of the data driver of the transfer destination.
As an other method of solving the above-mentioned problem, a low voltage differential signaling interface is employed. As its typical one, an interface using an RSDS (Reduced Swing Differential Signaling) system (which will be referred to as an RSDS interface) (refer to Patent Document 2) is used.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2003-84726A (FIG. 9)
[Patent Document 2]
JP Patent No. 3285332